Layout Preparation

Layout Preparation
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Layout Preparation

There are circuits whose functions are immune to layout.  Unfortunately - or maybe fortunately - even these need to be laid out on the printed circuit board in a thoughtful way today.  In the last 15 years EMC has become a major component of every design cycle I have seen.  As a circuit designer, one has an influence on EMC performance that is perhaps eclipsed only by the system engineer. 

I am not an ECAD technician or a EMC engineer, but I know the rules and tradeoffs involved in problem free layout.  Let me look over your design.  I will find the low impedance loops and find out where the Lenz Law voltages will express themselves in the circuit.  I may be able to suggest 'cross over' traces that will minimize the net loop area presented to a magnetic field.  I will suggest shielding, high quality distrubted capacitance between power planes and look for other opportunities to reduce circuit coupling on a single PC board or in a system.